// Verilog created by ORCAD Capture

module EP4CE6E144_2 
 ( 
		DATA0, 
		ASDO, 
		DB, 
		SD_D, 
		RD, 
		DSO_D, 
		NCSO, 
		WR, 
		DCLK, 
		DCOM, 
		A2V5, 
		FTCK, 
		FTDI, 
		FTDO, 
		FTMS, 
		SD_UDQM, 
		SD_A, 
		SD_CKE, 
		SD_CLK, 
		SD_WE, 
		SD_CAS, 
		SD_RAS, 
		SD_CS, 
		SD_BA0, 
		IO, 
		SD_BA1, 
		LED_FPGA, 
		ARB_D, 
		ARB_CLK, 
		TRIGIN, 
		DSO_CLK, 
		CPLD_CLK, 
		FPGA_INT, 
		AB, 
		SD_LDQM, 
		FPGA_CLK, 
		FPGA_CS );

inout	DATA0, ASDO, RD, NCSO, WR, DCLK, DCOM, A2V5, FTCK, FTDI, FTDO, FTMS;
inout	[0:15]	DB;
inout	[0:15]	SD_D;
inout	[0:7]	DSO_D;
inout	SD_UDQM, SD_CKE, SD_CLK, SD_WE, SD_CAS, SD_RAS, SD_CS, SD_BA0, SD_BA1, LED_FPGA, ARB_CLK, TRIGIN, DSO_CLK, CPLD_CLK, FPGA_INT;
inout	[0:11]	SD_A;
inout	[0:4]	IO;
inout	[0:7]	ARB_D;
inout	[16:18]	AB;
inout	SD_LDQM, FPGA_CLK, FPGA_CS;

initial
	begin
	end

endmodule
